64k x 18 synchronous cache tag ram pipelined output cy7c1358a/ gvt7164t18 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05121 rev. *a revised january 19, 2003 327 features ? fast match times: 4.5, 5.0, 6.0, and 7.0 ns fast clock speed: 133, 100, 83, and 75 mhz fast oe access times: 4.5 ns and 5.0 ns pipelined data comparator data input register load control by den 3.3v ?5% and +10% power supply 5v tolerant inputs except i/os clamp diodes to v ss at all inputs and outputs common data inputs and data outputs two chip enables for depth expansion address, data, and control registers internally self-timed write cycle automatic power-down for portable applications low profile 100-pin tqfp package functional description the cypress synchronous sram family employs high-speed, low-power cmos designs using advanced triple-layer polysil- icon, double-layer metal technology. each memory cell con- sists of four transistors and two high valued resistors. the gvt7164t18 sram integrates 65,536 x 18 sram cells with advanced synchronous peripheral circuitry and a 18-bit comparator for tag compare operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all ad- dresses, all data inputs, depth-expansion chip enables (ce and ce1), write enable (we ), and data input enable (den ). asynchronous inputs include the output enable (oe ) and the match output enable (moe ). the data outputs (q) and match output (match), enabled by oe and moe respectively, are also asynchronous. data inputs are registered with data input enable (den ) and chip enable pins (ce , ce1). the outputs of the data input registers are compared with data in the memory array and a match signal is generated. the match output is gated into a pipeline register and released to the match output pin at the next rising edge of clock (clk). the gvt7164t18 operates from a +3.3v power supply. all inputs and outputs are lvttl compatible. the device is ideally suited for address tag ram for up to 2 mb secondary cache. selection guide 7c1358a-133 7164t18-4 7c1358a-100 7164t18-5 7c1358a-83 7164t18-6 7c1358a-75 7164t18-7 maximum access time (ns) 4.5 5.0 6.0 7.0 maximum operating current (ma) 300 240 220 200 maximum cmos standby current (ma) 20 20 20 20
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 2 of 11 note: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams f or detailed information. dq we# ce# ce1 write output register oe# address register a 64k x 9 x 2 sram array output buffers input register dq1- dq18 dq dq dq enable clk latch latch den# compare dq moe# match 16 functional block diagram ? 64kx18 [1]
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 3 of 11 pin configurations 100-pin tqfp top view a nc nc v cc v ss nc dq9 dq8 dq7 v ss v cc dq6 dq5 v ss nc v cc nc dq4 dq3 v cc v ss dq2 dq1 nc nc v ss v cc nc nc nc nc nc nc v cc v ss nc nc dq10 dq11 v ss v cc dq12 dq13 v cc nc v ss dq14 dq15 v cc v ss dq16 dq17 dq18 nc v ss v cc nc nc nc a a ce ce1 nc nc nc nc nc v cc v ss clk nc we oe nc nc nc a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1358a/gvt7164t18 nc a a a a a a v ss match v ss v cc den moe a a a a a nc nc nc 1234567 a v cc aancancv cc b nc ce1 nca nc nc ce nc c nc nc nc v cc aanc d dq10 nc v ss nc v ss dq9 nc e nc dq11 v ss nc v ss nc dq8 f v cc nc v ss oe v ss dq7 v cc g nc dq12 nc nc v ss nc dq6 h dq13 nc v ss we v ss dq5 nc j v cc v cc nc v cc nc v cc v cc k nc dq14 v ss clk v ss nc dq4 l dq15 nc v ss nc nc dq3 nc m v cc dq16 v ss nc v ss nc v cc n dq17 nc v ss av ss dq2 nc p nc dq18 v ss av ss nc dq1 r nc a a v cc aanc t nc a a match a a zz u v cc den nc a moe nc v cc 119-lead bga top view
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 4 of 11 pin descriptions bga pins tqfp pins pin name type description 2a, 3a, 5a, 5c, 6c, 4n, 4p, 2r, 3r, 5r, 6r, 2t, 3t, 5t, 6t, 4u 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44 a input- synchronous addresses: these inputs are registered and must meet the set-up and hold times around the rising edge of clk. 4h 87 we input- synchronous write enable: this write enable is low for a write cycle and high for a read cycle. data i/o are high impedance one cycle after we = low is gated into register. 4k 89 clk input- synchronous clock: this signal registers the addresses, data, chip en- ables, write control and data input enable control input on its rising edge. all synchronous inputs must meet set-up and hold times around the clock ? s rising edge. 6b 98 ce input- synchronous chip enable: this active low input is used to enable the device. 2b 97 ce1 input- synchronous chip enable: this active high input is used to enable the device. 4f 86 oe input output enable: this active low asynchronous input enables the data output drivers. 2u 42 den input- synchronous data input enable: this active low input is used to control the update of data input registers. 4t 39 match output match output: match will be high if data in the data input registers match the data stored in the memory array, assum- ing moe being low. match will be low if data do not match. 5u 43 moe input match output enable: this active low asynchronous input enables the match output drivers. 7p, 6n, 6l, 7k, 6h, 7g, 6f, 7e, 6d, 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p 58, 59, 62, 63, 68, 69, 72, 73, 74, 8, 9, 12, 13, 18, 19, 22, 23, 24 dq1 ? dq18 input/ output data inputs/outputs: input data must meet set-up and hold times around the rising edge of clk. 1a, 7a, 4c, 1f, 7f, 1j, 2j, 4j, 6j, 7j, 1m, 7m, 4r, 1u, 7u 4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91 v cc supply power supply: +3.3v ? 5% and +10% 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p 5, 10, 17, 21, 26, 38, 40, 55, 60, 67, 71, 76, 90 v ss ground ground: gnd 4a, 6a, 1b, 3b, 4b, 5b, 7b, 1c, 2c, 3c, 7c, 2d, 4d, 7d, 1e, 4e, 6e, 2f, 1g, 3g, 4g, 6g, 2h, 7h, 3j, 5j, 1k, 6k, 2l, 4l, 5l, 7l, 4m, 6m, 2n, 7n, 1p, 6p, 1r, 7r, 1t, 7t, 3u, 6u 1-3, 6, 7, 14, 16, 25, 28-31, 49-53, 56, 57, 64, 66, 75, 78, 79, 83-85, 88, 92-96 nc - no connect: these signals are not internally connected.
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 5 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) voltage on v cc supply relative to v ss ......... ? 0.5v to +4.6v v in ........................................................... ? 0.5v to v cc +0.5v storage temperature (plastic) .................... ? 55 c to +150 c junction temperature ............................................... +150 c power dissipation.......................................................... 1.0w short circuit output current........................................ 50 ma notes: 2. x means ? don ? t care. ? h means logic high. l means logic low. 3. e =l is defined as ce = low and ce1 = high. e =h is defined as ce =high or ce1 = low. 4. all inputs except oe and moe must meet set-up and hold times around the rising edge (low to high) of clk. 5. for a write operation following a read operation, oe must be high before the input data required set-up time plus high-z time for oe and staying high throughout the input data hold time. 6. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 7. t a is the case temperature. 8. power supply ramp up should be monotonic. truth table [2, 3, 4, 5, 6] operation e we den moe oe match dq read cycle l h x x l - q write cycle lllxh-d fill write cycle l l h x h - high-z compare cycle l h l l h output d deselected cycle (match out) h x x l x h high-z deselected cycle h x x h x high-z high-z operating range range ambient temperature [7] v cc (8) com ? l 0 c to +70 c 3.3v ? 5%/+10%
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 6 of 11 electrical characteristics over the operating range parameter description test conditions min. max. unit v ihd input high (logic 1) voltage [9, 10] data inputs (dqxx) 2.0 v cc +0.5 v v ih all other inputs 2.0 4.6 v v il input low (logic 0) voltage [9, 10] ? 0.5 0.8 v il i input leakage current [11] 0v < v in < v cc ? 1 1 a il o output leakage current output(s) disabled, 0v < v out < v cc ? 1 1 a v oh output high voltage [9, 12] i oh = ? 4.0 ma 2.4 v v ol output low voltage [9, 12] i ol = 8.0 ma 0.4 v v cc supply voltage [9] 3.135 3.6 v parameter description conditions typ. 133 mhz/ -4 100 mhz/ -5 83 mhz/ -6 75 mhz/ -7 unit i cc power supply current: operating [13, 14, 15] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc = max.; outputs open 150 300 240 220 200 ma i sb2 cmos standby [14, 15] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 5 10101010ma i sb3 ttl standby [14, 15] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 10 20 20 20 20 ma i sb4 clock running [14, 15] device deselected; all inputs < v il or > v ih ; v cc = max.; clk cycle time > t kc min. 40 80 70 60 50 ma capacitance [16] parameter description test conditions typ. max. unit c i input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 4 5 pf c o input/output capacitance (dq) 7 8 pf thermal resistance description test conditions symbol tqfp typ. unit thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer pcb ja 25 c/w thermal resistance (junction to case) jc 9 c/w notes: 9. all voltages referenced to v ss (gnd). 10. overshoot: v ih +6.0v for t t kc /2. undershoot:v il ? 2.0v for t t kc /2. 11. capacitance derating applies to capacitance different from the load capacitance shown in part (a) of ac test loads. 12. ac i/o curves are available upon request. 13. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 14. ? device deselected ? means the device is in power-down mode as defined in the truth table. ? device selected ? means the device is active. 15. typical values are measured at 3.3v, 25 c, and 8.5-ns cycle time. 16. this parameter is sampled.
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 7 of 11 ac test loads and waveforms (17) dq 3.3v 317 ? 351 ? 5 pf (a) all input pulses 2.5v 0v 90% 10% 90% 10% 3 ns 3 ns (c) (b) vt = 1.5v dq z 0 = 50 ? 50 ? switching characteristics over the operating range [18] -4 133 mhz -5 100 mhz -6 83 mhz -7 75 mhz parameter description min. max. min. max. min. max. min. max. unit clock t kc clock cycle time 6.0 6.7 7.5 8.5 ns t kh clock high time 2.4 2.6 2.8 3.4 ns t kl clock low time 2.4 2.6 2.8 3.4 ns output times t kq clock to output valid 3.5 3.8 4.0 4.0 ns t km clock to match valid t kqx clock to output invalid 1.5 1.5 1.5 1.5 ns t kmx clock to match invalid t kqlz clock to output in low-z [16, 19, 20] 0 0 0 0 ns t kqhz clock to output in high-z [16, 19, 20] 1.5 6.0 1.5 6.7 1.5 7.5 1.5 8.5 ns t oeq oe to output valid [21] 3.5 3.5 3.8 3.8 ns t moem moe to match valid [21] t oelz oe to output in low-z [16, 19, 20] 0 0 0 0 ns t moelz moe to match in low-z [16, 19, 20] t oehz oe to output in high-z [16, 19, 20] 3.5 3.5 3.8 3.8 ns t moehz moe to match in high-z [16, 19, 20] set-up times t s address, controls, and data in [22] 1.5 1.5 1.5 2.0 ns hold times t h address, controls, and data in [22] 0.5 0.5 0.5 0.5 ns notes: 17. overshoot: vih(ac) cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 8 of 11 typical output buffer characteristics output high voltage pull-up current output low voltage pull-down current v oh (v) i oh (ma) min. i oh (ma) max. v ol (v) i ol (ma) min. i ol (ma) max. ? 0.5 ? 38 ? 105 ? 0.5 0 0 0 ? 38 ? 105 0 0 0 0.8 ? 38 ? 105 0.4 10 20 1.25 ? 26 ? 83 0.8 20 40 1.5 ? 20 ? 70 1.25 31 63 2.3 0 ? 30 1.6 40 80 2.7 0 ? 10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 switching waveforms read/write timing [23] notes: 23. ce active in this timing diagram means that all chip enables ce and ce1 are active. clk address we# ce# (see note) den# oe# dq a1 a2 a4 q(a1) q(a2) t s t h t kc a5 d(a5) d(a6) reads a8 a3 a6 a7 q(a3) q(a4) d(a7) d(a8) t kh t kl t kq t kqx t oehz t oeq t oelz t kqhz t kqlz writes
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 9 of 11 compare/fill write timing [23] switching waveforms (continued) clk address we# ce# den# oe# dq a1 t s t h t kc d(a1) t kh t kl t moelz t km moe# match a1 a2 d(a2) miss match high chip deselected fill write hit t moehz t moem t kmx
cy7c1358a/ gvt7164t18 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document #: 38-05121 rev. *a page 10 of 11 ordering information speed (mhz) ordering code package name package type operating range 133 cy7c1358a-133ac/ gvt7164t18t-4 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial 100 CY7C1358A-100AC/ gvt7164t18t-5 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack 83 cy7c1358a-83ac/ gvt7164t18t-6 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack 75 cy7c1358a-75ac/ gvt7164t18t-7 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1358a/ gvt7164t18 document #: 38-05121 rev. *a page 11 of 11 revision history document title: cy7c1358a/gvt7164t18 64k x 18 synchronous cache tag ram pipelined output document number: 38-05121 rev. ecn no. issue date orig. of change description of change ** 108312 09/25/01 bri new cypress spec ? converted from galvantech format. *a 123150 01/19/03 rbi updated power-up requirements in operating range and in ac test loads and waveforms
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